Latent image memory circuits have been disclosed in the prior art, which are capable of assuming a predefined binary state when power is turned on to the circuit. Prior art circuits employing bipolar transistor technology include U.S. Pat. Nos. 3,662,351; 3,801,967; and 3,820,086. Another approach to latent image memory circuits is described in U.S. Pat. No. 3,755,793 which discloses the use of both FET devices and charge coupled devices to obtain the latent image memory operation. Still another approach to achieving latent image memory operation employing single conductivity type FET transistor technology is described in U.S. Pat. No. 3,798,621, wherein FET devices can be selectively added to a basic cross-coupled RAM storage cell, to achieve both read/write and read only memory operations.
What is required is a more simplified circuit topology suitable for implementation in a complementary MOSFET technology.